A recent forum post out there in the middle of the Australian portion of the internet – AKA i4memory.com – led me to investigate the performance impact of a BIOS option on the EVGA X58 3X SLI Classified. The option labeled ‘MCH Strap’ would indicate that it changes the latencies of the MCH, like on previous Intel chipsets such as the P965, P35, X48 and so on. The only catch is that the Intel X58 chipset, does not have an MCH (Memory Controller Hub). The Intel X58 chipset is no longer responsible for the memory controller as Intel Core i7 processors now have a integrated memory controller – or IMC – on the CPU die.
This inherent difference in design of the chipset got me thinking, if there is no MCH, what is this setting actually changing? Apparently others were thinking the same thing as the question popped up in the i4memory.com forums. Needless to say, I took it upon myself to have a quick look, which you are reading right now…this very second, here at TechReaction.net.
Before we have a look at the testing, let’s go over the complete setup used for the testing, and discuss a little bit more about exactly what I am testing today, and why. First a couple photos of the setup followed by the list of hardware used.
|Motherboard:||EVGA X58 3X SLI Classified|
|Processor:||Intel Core i7 920 D0 (3845B026)|
|Processor Cooling:||Thermalright Ultra-120 eXtreme CU|
|Thermal Paste:||Arctic Silver Ceramique|
|Memory:||Corsair Dominator-GT 3x2GB PC3-15000 7-8-7-20 (TR3X6G1866C7GTF)|
|North Bridge Cooling:||Stock|
|South Bridge Cooling:||Stock|
|Power Supply:||Corsair HX1000W|
|Video Card:||EVGA GTX295 1792MB (GeForce 185.85)|
|Additional Fans:||Scythe Ultra Kaze 120MM 3000RPM 133.6CFM (DFS123812H-3000)|
|Hard Drive:||Seagate 7200.9 80GB SATAII 8MB cache|
|OS:||Windows Xp SP2 (custom n’light job)|
|Ambient Temperature:||23C ~ 25C|
This is primarily for Classified owners so I am just going to assume you are all familiar with the BIOS. On the main overclocking settings page is the option for the ‘MCH Strap’. There are a number of settings which are 2133, 1867, 1600, 1333, 1067, 800, AUTO, DRAM Ratio. On previous Intel chipsets, the MCH strap was responsible for various hidden chipset latency timings and a lower MCH strap would increase performance of the chipset, and subsequent memory subsystem. When adjusting the ‘MCH Strap’ setting on the Classified, the only visible changes are those to the memory sub-timings. A lower strap would result in tighter memory sub-timings. A higher strap setting and the sub-timings on the memory would loosen. Pretty straight forward…right?
One would assume so, but no one was sure in the i4memory.com forum discussion so I did this basic testing to see if there was anything being changed behind the scenes that we couldn’t see. The basic methodology is pretty straight forward. Set a high ‘MCH Strap’, then measure the systems performance and note the sub-timings. Set a low ‘MCH Strap’, then measure its performance the same way and also note the memory sub-timings that strap sets. Then simply set the higher ‘MCH Strap’ again, but this time manually adjust the memory sub-timings to that which the lower ‘MCH Strap’ set. If the performance is the same as the performance of the lower ‘MCH Strap’ setting, then we know there is nothing else going on that we can’t see.
I set the system up as outlined above. I decided on stock settings with the 2:12 memory ratio for no apparent reason really, I simply wanted to ensure I would have the ability to select a couple different ‘MCH Strap’ options. As it turns out, at these settings, the 1600 through to the 1067 ‘MCH Strap’ selection were the only ones available. That is why I only have results from those three straps. I also ran the AUTO option just to see what it would select. I used the Everest Ultimate and ScienceMark bandwidth test as well as a run of SPi 32M as that is the best way to see if any memory sub-system gains are had. I think that about covers the necessary details, so I’ll stop yapping and you can look at the results.
The results may appear almost identical but if we look close at the SPi times, there is a definite pattern there. From the higher ‘MCH Strap’ setting down to the lowest, we see the SPi time drop. This means we definitely have SPi gains from the lower ‘MCH Strap’ selections but that is primarily from the tighter memory sub-timings. Looking at the last result we can see that with the 1600 ‘MCH Strap’ selected and the sub-timings tightened manually to reflect the 1067 ‘MCH Strap’ selection, the result is the same time as the 1333 ‘MCH Strap’ selection. Considering there is only a 12 one-hundredths of a second difference between the 1067 and the 1333 ‘MCH Strap’ selection, I am going to conclude that the ‘MCH Strap’ option in the EVGA X58 3X SLI Classified BIOS is definitely just adjusting sub-timings and nothing more.
Obviously this wasn’t an exercise in exhaustive testing and I didn’t include any 3D testing but all indications of this setting were that it simply tightened and loosened the memory sub-timings. There is no reason to test 3D performance in my mind. Here is a full chart of all three runs of each setting, there was a reboot between each run.
To finish up I have included a sample from each ‘MCH Setting’ that was tested so you can see the memory sub-timings differences. If there are any further questions about this quick test, don’t hesitate to post a comment and I will do my best to answer. Thanks for reading.