Tech Reaction

So after an hour long battle with the image uploader, I think I can declare victory.

Relation between memory timings and frequency

You may have wondered which kit of RAM is better, the DDR 1066MHz at 5-5-5-15 or DDR 2133MHZ at 10-10-10-30. Some people will say the DDR 1066MHz at 5-5-5-15 is better because of the tighter timings others will say the DDR 2133MHz at 10-10-10-30 is better because of the higher frequency. The answer is the actual latency is exactly the same and the DDR 2133MHz at 10-10-10-30 is theoretically far superior.

Latency calculations

The fact is timings don’t really represent anything meaningful unless the frequency is known.

Meet the digital waveform.  (Click on it to view it in all of it’s glory.)

There is approximately 10 clock cycles over 1 second or 10Hertz represented in the image above.

Memory “timings” are really clock delays. By clock delays I mean that it will skip or delay the command by however many clock cycles the system has been set to skip. Our DDR 2133’s CAS is set to 10 which means that it will skip every 10 clocks before completing the request.

This means that a system running at 10Hertz with a clock delay of 10 will complete 1 instruction every second. Without the delay it would have completed 10 instructions per second.

If we were to set the clock speed to 5Hertz and the clock delay(timing) to 5 like in our DDR 1066 kit the system running at 5Hertz would also complete 1 instruction per second.

If you closely examine the info above you may notice that the actual latency(instructions per second) is equal to the inverse of the clock speed in single data rate multiplied by the clock delay(timing). The figures under the picture and to this point were all single data rate.

1/10Hertz*10=a delay between instructions of 1 second or 1 instruction per second

1/5Hertz*5=a delay between instructions of 1 second or 1 instruction per second

DDR 1066/2=SDR 533 inverse of 533 is 1/533*5=a delay between instructions of 0.00938 seconds or 106 instructions per second. Note that I used 1066 instead of 1066MHz. If you want the actual latencies of the real kits you will want to use the correct number which would be DDR 1,066,000,000.

You do the math for the DDR 2133 at 10-10-10-30. Unless I botched(it has been known to happen) this whole thing it should come out almost the same as the one above.

Now you are probably wonder why should you buy the DDR 2133MHz kit if the DDR 1066MHz kit has the same latency. The answer to that question is in the maximum possible bandwidth.

Bandwidth Calculations

The maximum possible bandwidth can be calculated by multiplying the frequency by the bus width.

The bus width for the desktop systems most of us are concerned with is 64Bits or 8 Bytes per channel. By using multiple memory channels the bus width is effectively multiplied by how ever many channels there are. A dual channel system uses dual 64Bit buses so 64Bits*2Channels=128Bits*frequency for the maximum possible bandwidth for our dual channel system. The same holds true for triple, quad, and however many channels your system uses.

Now using this new found knowledge lets calculate the maximum possible bandwidth of a dual channel kit of DDR running at 2133MHz. 2133MHz*2Channels*64Bits=273,024Megabits per second.

Now just about no one uses Megabits so convert it to Megabytes by dividing 273,024 by 8. 273,024Megabits/8=34,128Megabytes and for ease of use let’s divide it by 1024 to convert it to Gigabytes 34,128Megabytes/1024=33.328GB/s.

The DDR 1066MHz kit will be almost exactly half the maximum possible bandwidth of the DDR 2133MHz kit. You can either take my word for it or calculate it your self.

The real world bandwidth numbers won’t come anywhere close to the maximum possible bandwidth but the 2133MHz RAM will do better than the 1066MHz kit.

The Test

Let’s finish this up with a few Everest Cache and Memory Benchmarks. Even though Everest Cache and Memory Benchmark is more of a memory system benchmark(RAM to CPU not RAM memory controller) it should still work to prove the relation between frequency and latency numbers.

DDR 600 at 3-3-3-9 Latency is 81.7 nanoseconds

Now for the  DDR 1000 6-6-6-16, frequency has doubled along with the timing delays but latency is pretty much the same. The bandwidth is down because of the lower FSB speed.

If the people saying the DDR 1066MHz at 5-5-5-15 was lower latency than the DDR 2133MHz at 10-10-10-30 were correct, the memory latency number in the image above would have been much, much, higher.

Here’s a final image to prove that increased clock speed leads to increased bandwidth. (It didn’t in the above image because the slow FSB causes any extra bandwidth gained by increased frequency to be wasted.)  The lower latency is caused by tighter northbridge timings.

Conclusion

Don’t believe everything you hear on the Internet.