Tech Reaction

There seems to be some misunderstanding about what Hyper-Transport (HT-AMD), Quick Path Interconnect (QPI-Intel) and Front Side Bus (FSB-Intel and pre-A64 AMD) really are and their differences.

First we need to clear the air: Socket 775 is dying (FSB is DEAD)! The FSB can no longer adequately support the information flow. In the diagram below and with the data provided the problem is obvious, too much data for the old bus.

As can be seen all information must take one path on the older architecture.

The FSB will become more of a bottleneck with the advent of PCIe 3.0 and 32+ PCIe lanes and that is without considering the ever increasing memory bandwidth, highest current non JEDEC memory being DDR3 2200 (PC3 17600), and the expected release in 2012 of DDR4. The table’s below shows the maximum theoretical gigabytes per second transfer over the FSB, PCIe standards.

AHHHHH! The air is clear.

AMD and Intel are now on the same communication path.

For a comparison, the original Athlon64 X2 was bandwidth limited as compared to modern processors.

As a note: Hyper-Transport 3.0 extends the 1.4 GHz dual data rate (DDR) maximum clock of Hyper-Transport 2.0 to 1.8 GHz, 2.0 GHz, 2.4 GHz and 2.6 GHz, and delivers a maximum aggregate bandwidth of 41.6 gigabytes per second (GB/s) — a bandwidth increase of 86 percent over Hyper-Transport 2.0.( HyperTransport Consortium)

Intel is taking the the same path as AMD by separating Memory from I/O

Here is an example of a VIA chipset with HT for comparison

So gee whiz what are you really overclocking? Is it necessary?

On AMD systems there is one base clock (HT ref) for the CPU\HTT\Mem-Bus and Intel also uses a base clock (Host Clock) to achieve the desired effect.

What do QPI and HTT do and are they better? HTT and QPI do nothing for the CPU speed as they handle I/O-PCIe-ChipSet-MB (I will just call it I/O for ease) communications and are only in need of adjustment if you have a multiple video card solution or other special circumstances. They are better for several reasons; (1) Cost!! It is cheaper to build a fast, short and wide path for memory and a separate long, narrow and faster path for I/O. (2) Data integrity!! By having a bus that is maxed out with a limited data path there is an increased chance of error from data collision. (3) Speed!! When the bus is full (bottle necked) wait states are imposed and the CPU attempts to move the information through the bus as efficiently as possible. This will not be noticed in general use computing but in heavy multitasking and data/graphic/CPU intensive applications and games it will be noticed.

Special circumstances: video work, where video and audio data are constantly being manipulated causing frequent HDD accesses as well as the movement of massive amounts of data. This generally happens while working with CGI or special content creation.

QPI is a point-to-point processor interconnect developed by Intel in 2008 to replace their processor front side bus interface. CSI is defined as a variable width, point to point, packet-based interface implemented as two uni-directional links with low-voltage differential signaling. A full width CSI link is physically configured with 20 bit lanes in each direction; these bit lanes are divided into four quadrants of 5 bit lanes, providing 12-16GB/s of bandwidth in each direction.

The description of what is going on in the chatt is given above

HyperTransport (HT) is a state-of-art packet-based, high-bandwidth, scalable, low latency point-to-point interconnect technology that links processors to each other, processors to coprocessors and processors to I/O and peripheral controllers.

What does this have to do with overclocking? Not much. Don’t be afraid to lower multipliers when dealing with HT/QPI as there is generally no benefit.

Pictures/charts courtesy of: Google Images, HyperTransport Consortium and AMD