Four flattened copper heat-pipe contacts GPU directly for 0dB cooling experience– making it the COOLEST silent solution in the work. 95% larger thermal surface than normal design.
Super Alloy Power technology uses a special alloy formula in critical power delivery components for a 15% performance boost, 35°C cooler operation and 2.5 times longer lifespan.
The new and exclusive Super Alloy Power technology on ASUS graphics cards uses a special alloy formula which is highly-magnetic, heat-resistant and anti-corrosive. It delivers a more stable and quieter operation compared to the reference design – a welcome bonus sought after by performance seekers.
Intelligent system monitoring for efficient overclocking with an intuitive slide bar.
During overclocking, the Super Hybrid Engine acts as an intelligent controller to switch between high and low intensity power profiles in real time for 15% performance boost*. (Per ASUS and I do find some truth in this)
|Graphics Engine||AMD Radeon HD 6770|
|Bus Standard||PCI Express 2.1|
|Video Memory||GDDR5 1GB|
|Engine Clock||850 MHz|
|Memory Clock||4000 MHz ( 1000 MHz GDDR5 )|
|Resolution||D-Sub Max Resolution : 2048×1536
DVI Max Resolution : 2560×1600
|Interface||D-Sub Output : Yes x 1
DVI Output : Yes x 1 , Yes x 1 (via HDMI to DVI adaptor x 1)
HDMI Output : Yes x 1
HDCP Support : Yes
|Accessories||1 x Power cable
1 x HDMI to DVI adaptor
|Software||ASUS Utilities & Driver|
|ASUS Features||DirectCU Silent Series
Super Alloy Power
|Dimensions||11.42 ” x 6.69 ” x 1.97 ” Inch|
|Note||accessories:1x extended power cableTo have the best cooling performance, ASUS EAH6770 DC SL/2DI/1GD5 extends the Fansink to 2.5 slot, please check your motherboard slot before settle your EAH6770.|
The HD6770 is based on the Juniper XT that powers the HD5770 but there are some improvements. Adding OpenGL 4.1 (HD5770 has 3.2 support) support through hardware that will help the workstation user, Improved OpenCL support, native support for up to five displays (5770 was three), HDMI 1.4a support which has better signaling and bandwidth allowing for an improved feature set as well as a better 3D experience using the latest 3D televisions and Blu-ray players, H.264 MVC acceleration and support for third party Stereoscopic 3D middle ware. The 6770 is a definite improvement for the hardcore Videophile and light to medium gamer.
Moving to the video memory; most of which is geek speak and can be skipped by the majority of readers:
The GDDR5 SGRAM is a high speed dynamic random access memory designed for applications requiring high bandwidth.
GDDR5 devices contain the following number of bits:1Gb has 1,073,741,824 bits and sixteen banks. The GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high speed operation.
The device can be configured to operate in x32 mode or x16 (clamshell) mode. The mode is detected during device initialization.
The GDDR5 interface transfers two 32bit wide data words per WCK clock cycle to/from the I/O pins. Corresponding to the 8n prefetch a single write or read access consists of a 256 bit wide, two CKclock cycle data transfer at the internal memory core and eight corresponding 32 bit wide one half WCK clock cycle data transfers at the I/O pins.
The GDDR5 SGRAM operates from a differential clock CK and CK#.
Commands are registered at every rising edge of CK. Addresses are registered at every rising edge of CK and every rising edge of CK#. GDDR5 replaces the pulsed strobes (WDQS & RDQS) used in previous DRAMs such as GDDR4 with a free running differential forwarded clock (WCK/WCK#) with both input and output data registered and driven respectively at both edges of the forwarded WCK. Read and write accesses to the GDDR5 SGRAM are burst oriented; an access starts at a selected location and consists of a total of eight data words. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command and the next rising CK# edge are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command and the next rising CK# edge are used to select the bank and the column location for the burst access.
- Single ended interface for data, address and command
- Quarter data rate differential clock inputs CK/CK# for ADR/CMD
- Two half data rate differential clock inputs WCK/WCK#, each associated with two data bytes (DQ,DBI#,EDC)
- Double Data Rate (DDR) data (WCK)
- Single Data Rate (SDR) command (CK)
- Double Data Rate (DDR )addressing (CK)
- 16 internal banks
- 4 bank groups for tCCDL=3tCK
- 8n prefetch architecture: 256 bit per array read or write access
- Burst length: 8 only
- Programmable CAS latency: 5to20tCK
- Programmable WRITE latency:1to7tCK
- WRITE Data mask function via address bus (single/doublebytemask)
- Data bus inversion (DBI)&address bus inversion(ABI)
- Input/output PLL on/off mode
- Address training: address input monitoring by DQpins
- Data read and write training via READ FIFO
- READ FIFO pattern preload by LDFF command
- Direct write data load to READ FIFO by WRTR command
- Consecutive read of READ FIFO by RDTR command
- Read/Write data transmission integrity secured by cyclic redundancy check (CRC8)
- READ/WRITE EDC on/offmode
- Programmable EDC hold pattern for CDR
- Programmable CRC READ latency= 0 to 3t CK
- Programmable CRC WRITE latency=7 to 14t CK
- Low Power modes
- RDQS mode on EDC pin
- Optional on chip temperature sensor with readout
- Auto & self refresh modes
- Auto precharge option for each burst access
- 32ms, auto refresh (8k cycles)
- Temperature sensor controlled self refresh rate
- On die termination (ODT); nominal values of 60 ohm and 120 ohm
- Pseudo open drain (POD15) compatible outputs (40 ohm pull down, 60 ohm pull up)
- ODT and output drive strength auto calibration with external resistor ZQ pin (120ohm)
- Programmable termination and driver strength offsets
- Selectable external or internal VREF for data inputs; programmable offsets for internal VREF
- Separate external VREF for address/command inputs
- Vendor ID, FIFO depth and Density info fields for identification
- Mirror function with MF pin
- Boundary scan function with SEN pin
- 1.6V/1.5V+/(3%xVDD)V supply for device operation (VDD)
- 1.6V/1.5V+/(3%xVDDQ)V supply for I/O interface (VDDQ)
ASUS specs the memory at 4000 Mhz (1000) effective which allows some head room for overclocking while staying well within the memory manufacturers specifications. This will be tested.