Specifications

The GPU:

The HD6770 is based on the Juniper XT that powers the HD5770 but there are some improvements. Adding OpenGL 4.1 (HD5770 has 3.2 support) support through hardware that will help the workstation user, Improved OpenCL support, native support for up to five displays (5770 was three), HDMI 1.4a support which has better signaling and bandwidth allowing for an improved feature set as well as a better 3D experience using the latest 3D televisions and Blu-ray players, H.264 MVC acceleration and support for third party Stereoscopic 3D middle ware. The 6770 is a definite improvement for the hardcore Videophile and light to medium gamer.

GPU Specs:

• 76.8 GB/s memory bandwidth (maximum)
• Up to 1.36 TFLOPs compute power
• TeraScale 2 Unified Processing Architecture
  • 800 Stream Processors
  • 40 Texture Units
  • 64 Z/Stencil ROP Units
  • 16 Color ROP Units
• PCI Express® 2.1 x16 bus interface
• Full DirectX® 11 support
  • Shader Model 5.0
  • DirectCompute 11
  • Programmable hardware tessellation unit
  • Accelerated multi-threading
  • HDR texture compression
  • Order-independent transparency
• OpenGL 4.1 support
• Image quality enhancement technology
  • Up to 24x multi-sample and super-sample anti-aliasing modes
  • Adaptive anti-aliasing
  • 16x angle independent anisotropic texture filtering
  • 128-bit floating point HDR rendering
• AMD Eyefinity multi-display technology¹
  • Native support for up to 5 simultaneous displays
  • Independent resolutions, refresh rates, color controls, and video overlays
  • Display grouping
    • Combine multiple displays to behave like a single large display
• AMD App Acceleration²
  • OpenCL 1.1
  • DirectCompute 11
  • Accelerated video encoding, transcoding, and upscaling
• UVD 2 dedicated video playback accelerator
  • H.264
  • VC-1
  • MPEG-2
  • H.264 MVC (Blu-ray 3D)⁴
  • Adobe Flash
  • Enhanced Video Quality features
    • Advanced post-processing and scaling
    • Dynamic contrast enhancement and color correction
    • Brighter whites processing (Blue Stretch)
    • Independent video gamma control
    • Dynamic video range control
    • DXVA 1.0 & 2.0 support
• AMD HD3D technology⁴
  • Stereoscopic 3D display/glasses support
  • Blu-ray 3D support
  • Stereoscopic 3D gaming
  • 3rd party Stereoscopic 3D middleware software support
• AMD CrossFireX™ multi-GPU technology⁵
  • Dual GPU scaling
• Cutting-edge display support
  • Integrated DisplayPort Output
    • Max resolution: 2560×1600 per display
  • Integrated HDMI 1.4a with Stereoscopic 3D Frame Packing Format, Deep Color, xvYCC wide gamut support, and high bit-rate audio
    • Max resolution: 1920×1200
  • Integrated Dual-link DVI with HDCP
    • Max resolution: 2560×1600
  • Integrated VGA
    • Max resolution: 2048×1536
• Integrated HD audio controller
  • Output protected high bit rate 7.1 channel surround sound over HDMI or DisplayPort with no additional cables required
  • Supports AC-3, AAC, Dolby TrueHD and DTS Master Audio formats
• AMD PowerPlay™ power management technology³
  • Dynamic power management with low power idle state
  • Ultra-low power state support for multi-GPU configurations
• AMD Catalyst™ graphics and HD video configuration software
  • Unified graphics display drivers
    • Certified for Windows 7, Windows Vista, and Windows XP
  • AMD Catalyst^TM Control Center
  • Software application and user interface for setup, configuration, and accessing special features of AMD Radeon products.

Memory:

Moving to the video memory; most of which is geek speak and can be skipped by the majority of readers:

H5GQ1H24AFR

The GDDR5 SGRAM is a high speed dynamic random access memory designed for applications requiring high bandwidth.

GDDR5 devices contain the following number of bits:1Gb has 1,073,741,824 bits and sixteen banks. The GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high speed operation.

The device can be configured to operate in x32 mode or x16 (clamshell) mode. The mode is detected during device initialization.

The GDDR5 interface transfers two 32bit wide data words per WCK clock cycle to/from the I/O pins. Corresponding to the 8n prefetch a single write or read access consists of a 256 bit wide, two CKclock cycle data transfer at the internal memory core and eight corresponding 32 bit wide one half WCK clock cycle data transfers at the I/O pins.

The GDDR5 SGRAM operates from a differential clock CK and CK#.

Commands are registered at every rising edge of CK. Addresses are registered at every rising edge of CK and every rising edge of CK#. GDDR5 replaces the pulsed strobes (WDQS & RDQS) used in previous DRAMs such as GDDR4 with a free running differential forwarded clock (WCK/WCK#) with both input and output data registered and driven respectively at both edges of the forwarded WCK. Read and write accesses to the GDDR5 SGRAM are burst oriented; an access starts at a selected location and consists of a total of eight data words. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command and the next rising CK# edge are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command and the next rising CK# edge are used to select the bank and the column location for the burst access.

Features

• Single ended interface for data, address and command
• Quarter data rate differential clock inputs CK/CK# for ADR/CMD
• Two half data rate differential clock inputs WCK/WCK#, each associated with two data bytes (DQ,DBI#,EDC)
• Double Data Rate (DDR) data (WCK)
• Single Data Rate (SDR) command (CK)
• Double Data Rate (DDR )addressing (CK)
• 16 internal banks
• 4 bank groups for tCCDL=3tCK
• 8n prefetch architecture: 256 bit per array read or write access
• Burst length: 8 only
• Programmable CAS latency: 5to20tCK
• Programmable WRITE latency:1to7tCK
• WRITE Data mask function via address bus (single/doublebytemask)
• Data bus inversion (DBI)&address bus inversion(ABI)
• Input/output PLL on/off mode
• Address training: address input monitoring by DQpins
• WCK2CKclocktrainingwithphaseinformationbyEDCpins
• Data read and write training via READ FIFO
• READ FIFO pattern preload by LDFF command
• Direct write data load to READ FIFO by WRTR command
• Consecutive read of READ FIFO by RDTR command
• Read/Write data transmission integrity secured by cyclic redundancy check (CRC8)
• READ/WRITE EDC on/offmode
• Programmable EDC hold pattern for CDR
• Programmable CRC READ latency= 0 to 3t CK
• Programmable CRC WRITE latency=7 to 14t CK
• Low Power modes
• RDQS mode on EDC pin
• Optional on chip temperature sensor with readout
• Auto & self refresh modes
• Auto precharge option for each burst access
• 32ms, auto refresh (8k cycles)
• Temperature sensor controlled self refresh rate
• On die termination (ODT); nominal values of 60 ohm and 120 ohm
• Pseudo open drain (POD15) compatible outputs (40 ohm pull down, 60 ohm pull up)
• ODT and output drive strength auto calibration with external resistor ZQ pin (120ohm)
• Programmable termination and driver strength offsets
• Selectable external or internal VREF for data inputs; programmable offsets for internal VREF
• Separate external VREF for address/command inputs
• Vendor ID, FIFO depth and Density info fields for identification
• x32/x16modeconfigurationsetatpowerupwithEDCpin
• Mirror function with MF pin
• Boundary scan function with SEN pin
• 1.6V/1.5V+/(3%xVDD)V supply for device operation (VDD)
• 1.6V/1.5V+/(3%xVDDQ)V supply for I/O interface (VDDQ)

ASUS specs the memory at 4000 Mhz (1000) effective which allows some head room for overclocking while staying well within the memory manufacturers specifications. This will be tested.

Next: Gaming, OpenGL and transcoding Performance Benchmarks

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